1. Field of the Invention
The present invention relates to a wafer scale integration semiconductor device comprising a plurality of semiconductor circuit modules all integrated on an entire wafer or a fraction of a wafer and more particularly, to the architectures and methods to enable the economical implementation of a wafer-scale integrated circuit with high performance.
More specifically, this invention relates to a wafer-scale-integration system including (1) a novel configurable-interconnect architecture, (2) a novel high-speed parallel on-wafer bus system, (3) a unique layout that allows testing and configuration using simple probes, (4) a special coding method for establishing unique addresses for each circuit module, (5) a novel power supply switch, and (6) unique algorithms for configuring full-wafer or partial-wafer circuits.
2. Description of the Prior Art
In the fabrication of integrated circuits, a plurality of identical circuits such as memory cells are simultaneously fabricated on a wafer. The wafer is then broken along scribe lines into a plurality of dice or chips which are separately tested and packaged. Typically, yields from a given wafer are less than 100% since many of the chips are discarded. The wafer surface area is not used economically since substantial area is needed for scribe lines and bonding pads. The cost associated with the packaging of the individual chips represents a substantial portion of the total costs of the end products, and the "footprint" of a packaged chip is substantially larger than the chip itself. Furthermore, as the level of integration increases, the fabrication of progressively larger chips results in progressively lower yields at the same defect density. Many attempts have been made in the prior art to utilize the useful or operative circuits on a wafer while bypassing the inoperative circuits without physically separating the chips See, for example N. MacDonald et al, "200Mb Wafer Memory," IEEE 1989 ISSCC Technical Digest, pp. 240-241; P. J. Cavill et al, "Wafer-scale integration" Microelectronics Manufacturing Technology, pp. 55-59, May 1991; U.S. Pat. No 4,007,452 to M. E. Hoff, Jr., "Wafer Scale Integration System"; and U.S. Pat No. 4,038,648 to G. D. Chesley, "Self-Configurable Circuit Structure for Achieving Wafer Scale Integration. Alternative multi-chip-module approaches are also known that can approximate the high circuit density and high speed performance of true wafer scale integration. See, for example U.S. Pat. No. 4,866,501 "Wafer Scale Integration"; U.S. Pat. Nos. 4,884,122 and 4,937,203 "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer"; U.S. Pat. No. 4,907,062 "Semiconductor Wafer-Scale Integrated Device Composed of Interconnected Multiple Chips Each Having an Integration Circuit Chip . . . ". These approaches, however, do not address the yield and cost issues and are very expensive.
Generally, the operative circuits or devices on a wafer are electrically isolated from the inoperative devices through the use of one or more discretionary connections. These discretionary connections can be made using masks, fuses or fusible links. See, for example, U.S. Pat. Nos. 3,835,530 and 3,810,301. Special serial identify bus and circuitry was developed to address and operate operative modules with a relative connection method. This approach, like most other prior art approaches, assumes that the bus itself and its associated incremented circuitry are defect-free. In reality, however, as the buses traverse through the entire wafer, there is fairly high probability that there will be at least one defect that would render the whole wafer useless. Similarly, any defect in the power distribution buses, either open or short circuits, would have rendered useless the whole wafer or a significant portion of it. See, for example H. Stopper, "Wafer-Scale Integration", pp. 354-364, Electronic Material Handbook, ASM 1989. To minimize the defect and its impact on the buses themselves, one recent approach (MacDonald, cited above) relied on minimizing the number of wires in the bus and routed the bus in a spiral serial fashion through the wafer. This has the advantage of confining the impact of defect on the bus itself. Its serial nature, however, greatly limited performance as the data from any module must traverse through the spiral path to get to the outside.